Electrical Engineering Workflow: Nodal + RC Checks

Problem statement and target quantities

Solve a resistive node for branch currents, verify KCL, then derive first-order RC transfer behavior to connect circuit laws with frequency response.

Knowns: resistor values, source voltage, RC pair. Unknowns: node voltage/current split, cutoff frequency, gain/phase behavior, and loading sensitivity.

Assumptions and unit discipline

Nodal rows assume linear DC resistive behavior and explicit current sign convention.
RC rows assume small-signal first-order behavior without parasitics unless variant rows are added.
Loading must be modeled with Rload when downstream stage impedance is finite.
Use coherent units: ohm, F, V, Hz; convert to rad/s when required by derivations.

Derivation checkpoints

KCL: I1 - I2 - I3 = 0
Vn = (Vs/R1) / (1/R1 + 1/R2 + 1/R3)
H(s) = 1/(1 + sRC)
fc = 1/(2*pi*R*C)

Derive node equations from current conservation first, then map RC dynamics into transfer-function form for frequency interpretation.

1. Solve the node and branch currents

Start with a clear node diagram and commit to a current sign convention before solving anything. Then compute Vn, I1, I2, and I3. This converts the worksheet from algebra into circuit reasoning: what goes where, and why.

2. Verify KCL every time

The kcl_error row is your sanity gate. If it is not near zero, the rest of the worksheet is untrustworthy no matter how clean it looks. Keep this check in every derivative sheet so sign mistakes are caught immediately.

3. Add transfer function behavior

Once the DC network is consistent, move to the RC transfer rows: H(s), fc, gain, and phase. This is where you connect time-domain intuition (slow/fast response) with frequency-domain constraints (bandwidth and attenuation).

4. Freeze reusable scenarios

Preserve a known-good worksheet per topology (divider, RC stage, loaded stage) and fork it per design case. Reusing validated structure is safer than rebuilding equations from scratch under schedule pressure.

5. Note model limits and frequency units

Document that the RC rows are first-order linear approximations, then record whether you are reasoning in Hz or rad/s. Also state whether the output is unloaded or loaded. That keeps cutoff and phase interpretation consistent during design reviews.

Variable glossary and units

Symbol	Meaning	Typical unit
`R1,R2,R3`	Node-network resistances.	ohm
`Vs`	Source voltage.	V
`Vn`	Solved node voltage.	V
`R,C`	RC stage parameters.	ohm, F
`fc`	-3 dB cutoff frequency.	Hz

How to interpret the results

kcl_error_mag should stay very close to zero; if not, revisit current sign conventions.
gain_low_dB near 0 dB and gain_high_dB near -20 dB/dec confirms first-order behavior.
If loaded_fc_ratio deviates from 1, stage loading is materially changing bandwidth.

Common mistakes and how to avoid them

Mixing Hz and rad/s when moving between Bode formulas and transfer-function algebra.
Ignoring downstream loading and then overestimating cutoff frequency in real circuits.
Using a linear RC worksheet for nonlinear or clipping waveforms without qualification.

Worked example (interpreted)

Step 1: The nodal solve gives Vn=3.103 V and branch currents I1=4.044 mA, I2=3.103 mA, I3=0.940 mA.

Step 2: kcl_error evaluates to approximately zero, confirming current conservation with the chosen sign convention.

Step 3: The unloaded corner is fc=723.43 Hz, with about -0.043 dB at 0.1fc and -20.04 dB at 10fc.

Interpretation: this is the expected first-order low-pass shape; use the loaded variant rows before trusting bandwidth in cascaded stages.

When this model is invalid

Condition	Why invalid	Use instead
Output stage loading is non-negligible	Unloaded transfer function overestimates bandwidth.	Use `Rload`, `Req_loaded`, `fc_loaded` rows.
High-frequency parasitics dominate	Single-pole RC model omits ESR/ESL and layout effects.	Use measured/identified higher-order transfer model.
Large-signal nonlinear operation	Linear small-signal assumptions break near clipping/saturation.	Piecewise or nonlinear circuit simulation.

How to validate your worksheet

kcl_error_mag should be near zero.
gain_low_dB should stay near 0 dB and gain_high_dB near -20 dB/dec trend.
loaded_fc_ratio far from 1 indicates you must use loaded design equations.

Domain-specific variants in this template

The loaded RC branch models finite output loading so cutoff shift is explicit, not hidden in assumptions.

Practice problems (with answer outlines)

Practice 1: Nodal solve

Recompute Vn with R1=3.3k, R2=1.5k, R3=2.2k, Vs=9V.

Outline: Use conductance form of KCL at the node and solve algebraically for Vn.

Practice 2: Cutoff shift under load

With R=1k, C=220nF, and Rload=2k, compute loaded cutoff ratio.

Outline: Find Req=R||Rload, then compare fc_loaded/fc_unloaded.

Practice 3: Phase interpretation

Estimate phase at f=fc and explain why it is diagnostic for first-order behavior.

Outline: Substitute ωRC=1 into phase expression; expect approximately -45°.

References and standards

Sedra/Smith, Microelectronic Circuits (small-signal circuit fundamentals). Publisher page.
IEEE Std 181-2011 (pulse and transition terminology for waveform interpretation). IEEE standard.
Horowitz & Hill, The Art of Electronics (practical RC/filter behavior). Reference site.